The data phase continues until both parties are ready to complete the transfer and continue to the next data phase.
2.
The data phase continues until both parties are ready to complete the transfer and continue to the next data phase.
3.
A typical EEPROM serial protocol consists of three phases : OP-Code Phase, Address Phase and Data Phase.
4.
The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.
5.
A coherence-supporting target would avoid completing a data phase ( asserting TRDY # ) until it observed SDONE high.
6.
There are two sub-cases, which take the same amount of time, but one requires an additional data phase:
7.
This is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line.
8.
The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase.
9.
The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase.
10.
A simple transaction on the AHB consists of an address phase and a subsequent data phase ( without wait states : only two bus-cycles ).
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